Difference between revisions of "Paper:Sc2011Carlson"

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Line 18: Line 18:
 
   booktitle = {International Conference for High Performance Computing, Networking,
 
   booktitle = {International Conference for High Performance Computing, Networking,
 
Storage and Analysis (SC)},
 
Storage and Analysis (SC)},
   year = {2011},
+
   year = {2011}
  abstract = {Two major trends in high-performance computing, namely, larger numbers
 
of cores and the growing size of on-chip cache memory, are creating
 
significant challenges for evaluating the design space of future
 
processor architectures. Fast and scalable simulations are therefore
 
needed to allow for sufficient exploration of large multi-core systems
 
within a limited simulation time budget. By bringing together accurate
 
high-abstraction analytical models with fast parallel simulation,
 
architects can trade off accuracy with simulation speed to allow
 
for longer application runs, covering a larger portion of the hardware
 
design space. Interval simulation provides this balance between detailed
 
cycle-accurate simulation and one-IPC simulation, allowing long-running
 
simulations to be modeled much faster than with detailed cycle-accurate
 
simulation, while still providing the detail necessary to observe
 
core-uncore interactions across the entire system. Validations against
 
real hardware show average absolute errors within 25% for a variety
 
of multi-threaded workloads; more than twice as accurate on average
 
than one-IPC simulation. Further, we demonstrate scalable simulation
 
speed of up to 2.0 MIPS when simulating a 16-core system on an 8-core
 
SMP machine.}
 
 
}
 
}
 
</pre>
 
</pre>

Revision as of 05:38, 29 December 2011

Trevor E. Carlson, Wim Heirman, Lieven Eeckhout

Published at the International Conference for High Performance Computing, Networking, Storage and Analysis (SC'11)

Abstract

Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast and scalable simulations are therefore needed to allow for sufficient exploration of large multi-core systems within a limited simulation time budget. By bringing together accurate high-abstraction analytical models with fast parallel simulation, architects can trade off accuracy with simulation speed to allow for longer application runs, covering a larger portion of the hardware design space. Interval simulation provides this balance between detailed cycle-accurate simulation and one-IPC simulation, allowing long-running simulations to be modeled much faster than with detailed cycle-accurate simulation, while still providing the detail necessary to observe core-uncore interactions across the entire system. Validations against real hardware show average absolute errors within 25% for a variety of multi-threaded workloads; more than twice as accurate on average as one-IPC simulation. Further, we demonstrate scalable simulation speed of up to 2.0 MIPS when simulating a 16-core system on an 8-core SMP machine.

Full text

Full paper PDF

Bibtex entry

@INPROCEEDINGS{carlson2011etloafsaapms,
  author = {Trevor E. Carlson and Wim Heirman and Lieven Eeckhout},
  title = {Sniper: Exploring the Level of Abstraction for Scalable and Accurate
	Parallel Multi-Core Simulations},
  booktitle = {International Conference for High Performance Computing, Networking,
	Storage and Analysis (SC)},
  year = {2011}
}