Publications using Sniper
Ioannis Stamelakos, Sotirios Xydis, Gianluca Palermo and Cristina Silvano. Variation Aware Voltage Island Formation for Power Efficient Near-Threshold Manycore Architectures. 14th Asia and South Pacific Design Automation Conference (ASP-DAC).
K. Van Craeynest, S. Akram, W. Heirman, A. Jaleel, L. Eeckhout. Fairness-Aware Scheduling on Single-ISA Heterogeneous Multi-Cores. International Conference on Parallel Architectures and Compilation Techniques (PACT).
Sparsh Mittal, Zhao Zhang, Jeffrey Vetter, FlexiWay: A Cache Energy Saving Technique Using Fine-grained Cache Reconfiguration. International Conference on Computer Design (ICCD).
Sparsh Mittal, Yanan Cao, and Zhao Zhang. MASTER: A Multicore Cache Energy Saving Technique using Dynamic Cache Reconfiguration. IEEE Transactions on VLSI Systems.
Bharathwaj Raghunathan, Yatish Turakhia, Siddharth Garg and Diana Marculescu. Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE).
Yatish Turakhia, Bharathwaj Raghunathan, Siddharth Garg and Diana Marculescu. HaDeS: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multi-processors. ACM/IEEE Design Automation Conference (DAC).
Sparsh Mittal and Zhao Zhang. Palette: A cache leakage energy saving technique for green computing. In Charlie Catlett, Wolfgang Gentzsch, Lucio Grandinetti, Gerhard Joubert, and Jose Vazquez-Poletti, editors, HPC: Transition Towards Exascale Processing, Series: Advances in Parallel Computing. IOS Press.
Sparsh Mittal and Zhao Zhang. ESTO: A Performance Estimation Approach for Efficient Design Space Exploration. Design Contest at 26th International Conference for VLSI Design.
Trevor E. Carlson; Wim Heirman; Lieven Eeckhout. Sampled Simulation of Multi-Threaded Applications. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Best Paper.
Sparsh Mittal; Zhao Zhang; Yanan Cao. CASHIER: A Cache Energy Saving Technique for QoS Systems. IEEE 26th International Conference on VLSI Design.
Wim Heirman; Souradip Sarkar; Trevor E. Carlson; Ibrahim Hur; Lieven Eeckhout. Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization. International Conference on Parallel Architectures and Compilation Techniques (PACT).
Trevor E. Carlson; Wim Heirman; Lieven Eeckhout. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation. International Conference for High Performance Computing, Networking, Storage and Analysis (SC).
Wim Heirman; Trevor E. Carlson; Shuai Che; Kevin Skadron; Lieven Eeckhout. Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-Threaded Workloads. International Symposium on Workload Characterization (IISWC).
Ma Zhe; Trevor E. Carlson; Wim Heirman; Lieven Eeckhout. Evaluating application vulnerability to soft errors in multi-level cache hierarchy. 4th Workshop on Resiliency in High Performance Computing (Resilience) in Clusters, Clouds, and Grids.
Wim Heirman; Trevor E. Carlson; Souradip Sarkar; Pieter Ghysels; Wim Vanroose; Lieven Eeckhout. Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. International Conference on Parallel Computing (ParCo).