Difference between revisions of "The Sniper Multi-Core Simulator"

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Sniper is a parallel, fast and accurate x86-64 micro-architectural simulator with speeds of up to 2 MIPS.  The goal of this simulator is to allow fast simulation, while allowing both hardware architects and software developers the freedom to choose the level of abstraction needed for their immediate goal. Our fast and accurate core model, the interval core model, allows for a detailed view of application performance while providing good simulation speed. In addition to the detailed out-of-order core model, we provide modern branch predictors and shared-cache memory models. The simulator is being developed at Ghent University's Performance Lab in conjunction with the Intel ExaScience Lab in Leuven, Belgium and was originally based on the [http://groups.csail.mit.edu/carbon/graphite Graphite] simulation framework.
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At Ghent University and the Intel ExaScience Lab, we have been working on
 +
a next generation multi-threaded, high-speed and accurate
 +
simulator, called [http://www.exascience.com/wp-content/uploads/2011/09/Sc2011carlson-final.pdf Sniper].  This micro-architecture simulator is
 +
based on the [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf interval core model] and the [http://groups.csail.mit.edu/carbon/graphite Graphite] simulation
 +
infrastructure, allowing for fast and accurate simulation and for
 +
trading off simulation speed for accuracy to allow a range of flexible
 +
simulation options when exploring different micro-architectures.
 +
Using this methodology, we are able to achieve good
 +
accuracy against hardware for 16-thread applications, with a speed of
 +
up to 2 MIPS.
  
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You can find additional information on the simulator and its components in our recently accepted SC2011 paper [ [http://www.exascience.com/wp-content/uploads/2011/09/Sc2011carlson-final.pdf pdf] ].
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The Sniper simulator allows one to perform timing simulations for
 +
multi-threaded, shared-memory applications with 10s to 100+ cores,
 +
at a high speed when compared to existing simulators.  The main
 +
feature of the simulator is its core model which is based on the [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf interval core model],
 +
a fast mechanistic core model.  The interval model allows for
 +
faster simulations that typical cycle-accurate simulators by jumping
 +
past regions when the core is idle because of long latency operations.
 +
 
 +
This simulator, and the interval core model, is useful for uncore
 +
and system-level studies that require more detail than the typical
 +
one-IPC models.  As an added benefit, the interval core model allows
 +
the generation of CPI stacks, which shows the number of cycles lost
 +
due to different characteristics of the system, like the cache
 +
hierarchy or branch predictor, to be easily understood.
  
 
=== Features ===
 
=== Features ===
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<div class="floatright">http://snipersim.org/w/images/cpi-splash2-fft-med.png</div>
 
<div class="floatright">http://snipersim.org/w/images/cpi-splash2-fft-med.png</div>
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* The interval performance model [ [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf pdf] ]
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In addition to the main features mentioned above, we have updated
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** Allows for fast and accurate simulation
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the base simulation infrastructure to allow for simulating a larger
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* CPI stack generation [[CPI Stacks|in three easy steps]]
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set of workloads on more recent simulated hardware.  Here is the full
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** Shows where your cycles are going
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set of some of the recently added features:
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* Multithreaded simulator for multithreaded applications
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* [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf Interval core model]
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* [[CPI Stacks]] to gain insight into lost cycles
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* Multithreaded, x86-64 support
 
* Validated against the Intel Core 2 micro-architecture
 
* Validated against the Intel Core 2 micro-architecture
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* Shared caches, modern branch predictors
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* Full DVFS support
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* DVFS support
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* Shared and private caches
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* Successfully runs SPLASH-2, PARSEC, Rodinia, and SPEC OpenMP
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* [http://dx.doi.org/10.1109/ISPASS.2009.4919652 Modern branch predictor]
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* [[License|Licensing]]: MIT License (academic use only license for the interval core model)
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* OpenMP support
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* [[Sniper Features|Many more features]]
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* Runs SPLASH-2, Rodinia, SPEC OpenMP and most of PARSEC
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* SimAPI for changing the simulator's behavior at runtime
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* Easy debugging of applications and the simulator
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* Multiple Linux-OS support (Redhat/Debian/Ubuntu/etc.)
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* Open source software, [[License|licensed]] under the MIT and Interval Academic License
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* [[Sniper Features|Additional features]]
 +
 
 +
You can find additional information on the simulator and its components in our recently accepted SC2011 paper [ [http://www.exascience.com/wp-content/uploads/2011/09/Sc2011carlson-final.pdf pdf] ].
  
 
=== Getting started ===
 
=== Getting started ===

Revision as of 02:10, 29 November 2011

At Ghent University and the Intel ExaScience Lab, we have been working on a next generation multi-threaded, high-speed and accurate simulator, called Sniper. This micro-architecture simulator is based on the interval core model and the Graphite simulation infrastructure, allowing for fast and accurate simulation and for trading off simulation speed for accuracy to allow a range of flexible simulation options when exploring different micro-architectures. Using this methodology, we are able to achieve good accuracy against hardware for 16-thread applications, with a speed of up to 2 MIPS.

The Sniper simulator allows one to perform timing simulations for multi-threaded, shared-memory applications with 10s to 100+ cores, at a high speed when compared to existing simulators. The main feature of the simulator is its core model which is based on the interval core model, a fast mechanistic core model. The interval model allows for faster simulations that typical cycle-accurate simulators by jumping past regions when the core is idle because of long latency operations.

This simulator, and the interval core model, is useful for uncore and system-level studies that require more detail than the typical one-IPC models. As an added benefit, the interval core model allows the generation of CPI stacks, which shows the number of cycles lost due to different characteristics of the system, like the cache hierarchy or branch predictor, to be easily understood.

Features

cpi-splash2-fft-med.png

In addition to the main features mentioned above, we have updated the base simulation infrastructure to allow for simulating a larger set of workloads on more recent simulated hardware. Here is the full set of some of the recently added features:

  • Interval core model
  • CPI Stacks to gain insight into lost cycles
  • Multithreaded, x86-64 support
  • Validated against the Intel Core 2 micro-architecture
  • Full DVFS support
  • Shared and private caches
  • Modern branch predictor
  • OpenMP support
  • Runs SPLASH-2, Rodinia, SPEC OpenMP and most of PARSEC
  • SimAPI for changing the simulator's behavior at runtime
  • Easy debugging of applications and the simulator
  • Multiple Linux-OS support (Redhat/Debian/Ubuntu/etc.)
  • Open source software, licensed under the MIT and Interval Academic License
  • Additional features

You can find additional information on the simulator and its components in our recently accepted SC2011 paper [ pdf ].

Getting started

Discussion list

Please send any questions or comments to: snipersim [at] groups [dot] google [dot] com . You can also visit our Google Groups page to subscribe to the list and search through the archive of previous messages.

Who we are

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