Difference between revisions of "The Sniper Multi-Core Simulator"

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a next generation multi-threaded, high-speed and accurate
 
a next generation multi-threaded, high-speed and accurate
 
simulator, called [http://www.exascience.com/wp-content/uploads/2011/09/Sc2011carlson-final.pdf Sniper].  This micro-architecture simulator is
 
simulator, called [http://www.exascience.com/wp-content/uploads/2011/09/Sc2011carlson-final.pdf Sniper].  This micro-architecture simulator is
based on the [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf interval core model] and the [http://groups.csail.mit.edu/carbon/graphite Graphite] simulation
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based on the [[Interval Model|interval core model]] and the [http://groups.csail.mit.edu/carbon/graphite Graphite] simulation
 
infrastructure, allowing for fast and accurate simulation and for
 
infrastructure, allowing for fast and accurate simulation and for
 
trading off simulation speed for accuracy to allow a range of flexible
 
trading off simulation speed for accuracy to allow a range of flexible
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multi-threaded, shared-memory applications with 10s to 100+ cores,
 
multi-threaded, shared-memory applications with 10s to 100+ cores,
 
at a high speed when compared to existing simulators.  The main
 
at a high speed when compared to existing simulators.  The main
feature of the simulator is its core model which is based on the [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf interval core model],
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feature of the simulator is its core model which is based on the [[Interval Model|interval core model]],
 
a fast mechanistic core model.  The interval model allows for
 
a fast mechanistic core model.  The interval model allows for
 
faster simulations that typical cycle-accurate simulators by jumping
 
faster simulations that typical cycle-accurate simulators by jumping
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set of workloads on more recent simulated hardware.  Here is the full
 
set of workloads on more recent simulated hardware.  Here is the full
 
set of some of the recently added features:
 
set of some of the recently added features:
* [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf Interval core model]
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* [[Interval Model|Interval core model]]
 
* [[CPI Stacks]] to gain insight into lost cycles
 
* [[CPI Stacks]] to gain insight into lost cycles
 
* Multithreaded, x86-64, SSE
 
* Multithreaded, x86-64, SSE

Revision as of 02:36, 29 November 2011

At Ghent University and the Intel ExaScience Lab, we have been working on a next generation multi-threaded, high-speed and accurate simulator, called Sniper. This micro-architecture simulator is based on the interval core model and the Graphite simulation infrastructure, allowing for fast and accurate simulation and for trading off simulation speed for accuracy to allow a range of flexible simulation options when exploring different micro-architectures. Using this methodology, we are able to achieve good accuracy against hardware for 16-thread applications, with a speed of up to 2 MIPS.

The Sniper simulator allows one to perform timing simulations for multi-threaded, shared-memory applications with 10s to 100+ cores, at a high speed when compared to existing simulators. The main feature of the simulator is its core model which is based on the interval core model, a fast mechanistic core model. The interval model allows for faster simulations that typical cycle-accurate simulators by jumping past regions when the core is idle because of long latency operations.

This simulator, and the interval core model, is useful for uncore and system-level studies that require more detail than the typical one-IPC models. As an added benefit, the interval core model allows the generation of CPI stacks, which shows the number of cycles lost due to different characteristics of the system, like the cache hierarchy or branch predictor, to be easily understood.

Features

cpi-splash2-fft-lg.png

In addition to the main features mentioned above, we have updated the base simulation infrastructure to allow for simulating a larger set of workloads on more recent simulated hardware. Here is the full set of some of the recently added features:

  • Interval core model
  • CPI Stacks to gain insight into lost cycles
  • Multithreaded, x86-64, SSE
  • Validated against the Intel Core 2 micro-architecture
  • Full DVFS support
  • Shared and private caches
  • Modern branch predictor
  • OpenMP support
  • Runs SPLASH-2, Rodinia, SPEC OpenMP and most of PARSEC
  • SimAPI for changing the simulator's behavior at runtime
  • Easy debugging of applications and the simulator
  • Multiple Linux-OS support (Redhat/Debian/Ubuntu/etc.)
  • Open source software, licensed under the MIT and Interval Academic License
  • Additional features

You can find additional information on the simulator and its components in our recently accepted SC2011 paper [ pdf ].

Getting started

Discussion list

Please send any questions or comments to: snipersim [at] groups [dot] google [dot] com . You can also visit our Google Groups page to subscribe to the list and search through the archive of previous messages.

Team Members

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