Interval Simulation - Revision history

Tcarlson at 13:47, 29 May 2012

2012-05-29T13:47:35Z

Tcarlson at 13:47, 29 May 2012

2012-05-29T13:47:17Z

Tcarlson at 13:47, 29 May 2012

2012-05-29T13:47:05Z

Wheirman at 12:35, 29 December 2011

2011-12-29T12:35:18Z

Wheirman at 12:34, 29 December 2011

2011-12-29T12:34:49Z

Wheirman: moved Interval Model to Interval Simulation

2011-11-29T10:00:21Z

moved Interval Model to Interval Simulation

Wheirman at 10:00, 29 November 2011

2011-11-29T10:00:04Z

Wheirman at 09:48, 29 November 2011

2011-11-29T09:48:54Z

Wheirman: Created page with "Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010 [..."

2011-11-29T09:34:35Z

Created page with "Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010 [..."

New page

Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010 [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf PDF]

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 [[File:Interval.png|right|500px]]
-Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (like branch mispredictions, cache and TLB misses, serialization instructions, etc.) divide the smooth streaming of instructions through the pipeline into so called intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
+Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (like branch mispredictions, cache and TLB misses, serialization instructions, etc.) divide the smooth streaming of instructions through the pipeline into intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
 the miss events; the analytical model derives the timing for each interval. The cooperation between the mechanistic analytical model and the miss event simulators enables the modeling of the tight performance entanglement between co-executing threads on multi-core processors.

@@ Line 1: / Line 1: @@
 [[File:Interval.png|right|500px]]
-Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (like branch mispredictions, cache and TLB misses, serialization instructions, etc) divide the smooth streaming of instructions through the pipeline into so called intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
+Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (like branch mispredictions, cache and TLB misses, serialization instructions, etc.) divide the smooth streaming of instructions through the pipeline into so called intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
 the miss events; the analytical model derives the timing for each interval. The cooperation between the mechanistic analytical model and the miss event simulators enables the modeling of the tight performance entanglement between co-executing threads on multi-core processors.

@@ Line 1: / Line 1: @@
 [[File:Interval.png|right|500px]]
-Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (branch mispredictions, cache and TLB misses) divide the smooth streaming of instructions through the pipeline into so called intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
+Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (like branch mispredictions, cache and TLB misses, serialization instructions, etc) divide the smooth streaming of instructions through the pipeline into so called intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
 the miss events; the analytical model derives the timing for each interval. The cooperation between the mechanistic analytical model and the miss event simulators enables the modeling of the tight performance entanglement between co-executing threads on multi-core processors.

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 the miss events; the analytical model derives the timing for each interval. The cooperation between the mechanistic analytical model and the miss event simulators enables the modeling of the tight performance entanglement between co-executing threads on multi-core processors.
 The multi-core interval simulator models the timing for the individual cores. The simulator maintains a ''window'' of instructions for each simulated core. This window of instructions corresponds to the reorder buffer of a superscalar out-of-order processor, and is used to determine miss events that are overlapped by long-latency load misses. The functional simulator feeds instructions into this window at the window tail. Core-level progress (i.e., timing simulation) is derived by considering the instruction at the window head. In case of an I-cache miss, the core simulated time is increased by the miss latency. In case of a branch misprediction, the branch resolution time plus the front-end pipeline depth is added to the core simulated time, i.e., this is to model the penalty for executing the chain of dependent instructions leading to the mispredicted branch plus the number of cycles needed to refill the front-end pipeline. In case of a long-latency load (i.e., a last-level cache miss or cache coherence miss), we add the miss latency to the core sim-ulated time, and we scan the window for independent miss events (cache misses and branch mispredictions) that are overlapped by the long-latency load - second-order effects. For a serializing instruction, we add the window drain time to the simulated core time. If none of the above cases applies, we dispatch instructions at the effective dispatch rate, which takes into account inter-instruction dependencies as well as their execution latencies.
 Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. [[Paper:Hpca2010Genbrugge|Interval Simulation: Raising the Level of Abstraction in Architectural Simulation]]. Proceedings of HPCA, pp. 307-318, Feb 2010

@@ Line 1: / Line 1: @@
 [[File:Interval.png|right|500px]]
-Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This
+Interval simulation is a recently proposed simulation approach for simulating multi-core and multiprocessor systems at a higher level of abstraction compared to current practice of detailed cycle-accurate simulation. This technique leverages a mechanistic analytical model to abstract core performance by driving the timing simulation of an individual core without the detailed tracking of individual instructions through the core's pipeline stages. The foundation of the model is that miss events (branch mispredictions, cache and TLB misses) divide the smooth streaming of instructions through the pipeline into so called intervals. Branch predictor, memory hierarchy, cache coherence and interconnection network simulators determine
-longstanding problem is further exacerbated in the multicore processor era. Existing solutions address the simulation problem by either sampling the simulated instruction
+the miss events; the analytical model derives the timing for each interval. The cooperation between the mechanistic analytical model and the miss event simulators enables the modeling of the tight performance entanglement between co-executing threads on multi-core processors.
-Interval simulation raises
+The multi-core interval simulator models the timing for the individual cores. The simulator maintains a ''window'' of instructions for each simulated core. This window of instructions corresponds to the reorder buffer of a superscalar out-of-order processor, and is used to determine miss events that are overlapped by long-latency load misses. The functional simulator feeds instructions into this window at the window tail. Core-level progress (i.e., timing simulation) is derived by considering the instruction at the window head. In case of an I-cache miss, the core simulated time is increased by the miss latency. In case of a branch misprediction, the branch resolution time plus the front-end pipeline depth is added to the core simulated time, i.e., this is to model the penalty for executing the chain of dependent instructions leading to the mispredicted branch plus the number of cycles needed to refill the front-end pipeline. In case of a long-latency load (i.e., a last-level cache miss or cache coherence miss), we add the miss latency to the core sim-ulated time, and we scan the window for independent miss events (cache misses and branch mispredictions) that are overlapped by the long-latency load - second-order effects. For a serializing instruction, we add the window drain time to the simulated core time. If none of the above cases applies, we dispatch instructions at the effective dispatch rate, which takes into account inter-instruction dependencies as well as their execution latencies.
-Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010. [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf PDF]
+Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. [[Paper:Hpca2010Genbrugge|Interval Simulation: Raising the Level of Abstraction in Architectural Simulation]]. Proceedings of HPCA, pp. 307-318, Feb 2010

← Older revision	Revision as of 10:00, 29 November 2011
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← Older revision		Revision as of 10:00, 29 November 2011
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		+	Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This
		+	longstanding problem is further exacerbated in the multicore processor era. Existing solutions address the simulation problem by either sampling the simulated instruction
		+	stream or by mapping the simulation models on FPGAs;
		+	these approaches achieve substantial simulation speedups
		+	while simulating performance in a cycle-accurate manner.

−	Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010 [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf PDF]	+	Interval simulation raises
		+	the level of abstraction and replaces the core-level cycleaccurate simulation model by a mechanistic analytical
		+	model. The analytical model estimates core-level performance by analyzing intervals, or the timing between two
		+	miss events (branch mispredictions and TLB/cache misses);
		+	the miss events are determined through simulation of the
		+	memory hierarchy, cache coherence protocol, interconnection network and branch predictor. By raising the level of
		+	abstraction, interval simulation reduces both development
		+	time and evaluation time.
		+
		+	Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010. [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf PDF]

← Older revision		Revision as of 09:48, 29 November 2011
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		+	[[File:Interval.png\|right\|500px]]
		+
	Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010 [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf PDF]		Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout. Interval Simulation: Raising the Level of Abstraction in Architectural Simulation. Proceedings of HPCA, pp. 307-318, Feb 2010 [http://users.elis.ugent.be/~leeckhou/papers/hpca10.pdf PDF]