Paper:Taco2014Carlson - Revision history

Tcarlson at 09:14, 26 January 2015

2015-01-26T09:14:40Z

Tcarlson at 09:14, 26 January 2015

2015-01-26T09:14:10Z

Tcarlson: Created page with "{{DISPLAYTITLE:An Evaluation of High-Level Mechanistic Core Models}} Trevor E. Carlson, Wim Heirman, Lieven Eeckhout ''Published in the ACM Transactions on Architecture and Code..."

2015-01-26T09:11:53Z

Created page with "{{DISPLAYTITLE:An Evaluation of High-Level Mechanistic Core Models}} Trevor E. Carlson, Wim Heirman, Lieven Eeckhout ''Published in the ACM Transactions on Architecture and Code..."

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{{DISPLAYTITLE:An Evaluation of High-Level Mechanistic Core Models}}
Trevor E. Carlson, Wim Heirman, Lieven Eeckhout

''Published in the ACM Transactions on Architecture and Code Optimization ([http://taco.acm.org TACO])''

===Abstract===
Large core counts and complex cache hierarchies are increasing the burden placed on commonly used simulation and modeling techniques. Although analytical models provide fast results, they do not apply to complex, many-core shared-memory systems. In contrast, detailed cycle-level simulation can be accurate but also tends to be slow, which limits the number of configurations that can be evaluated. A middle ground is needed that provides for fast simulation of complex many-core processors while still providing accurate results.

In this article, we explore, analyze, and compare the accuracy and simulation speed of high-abstraction core models as a potential solution to slow cycle-level simulation. We describe a number of enhancements to interval simulation to improve its accuracy while maintaining simulation speed. In addition, we introduce the instruction-window centric (IW-centric) core model, a new mechanistic core model that bridges the gap between interval simulation and cycle-accurate simulation by enabling high-speed simulations with higher levels of detail. We also show that using accurate core models like these are important for memory subsystem studies, and that simple, naive models, like a one-IPC core model, can lead to misleading and incorrect results and conclusions in practical design studies. Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.

===Bibtex entry===
<pre>@ARTICLE{carlson2014aeohmcm,
author = {Trevor E. Carlson and Wim Heirman and Stijn Eyerman and Ibrahim Hur
and Lieven Eeckhout},
title = {An Evaluation of High-Level Mechanistic Core Models},
journal = {ACM Transactions on Architecture and Code Optimization (TACO)},
year = {2014},
address = {New York, NY, USA},
articleno = {5},
doi = {10.1145/2629677},
issn = {1544-3566},
issue_date = {April 2014},
numpages = {23},
publisher = {ACM}
}
</pre>

← Older revision		Revision as of 09:14, 26 January 2015
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	In this article, we explore, analyze, and compare the accuracy and simulation speed of high-abstraction core models as a potential solution to slow cycle-level simulation. We describe a number of enhancements to interval simulation to improve its accuracy while maintaining simulation speed. In addition, we introduce the instruction-window centric (IW-centric) core model, a new mechanistic core model that bridges the gap between interval simulation and cycle-accurate simulation by enabling high-speed simulations with higher levels of detail. We also show that using accurate core models like these are important for memory subsystem studies, and that simple, naive models, like a one-IPC core model, can lead to misleading and incorrect results and conclusions in practical design studies. Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.		In this article, we explore, analyze, and compare the accuracy and simulation speed of high-abstraction core models as a potential solution to slow cycle-level simulation. We describe a number of enhancements to interval simulation to improve its accuracy while maintaining simulation speed. In addition, we introduce the instruction-window centric (IW-centric) core model, a new mechanistic core model that bridges the gap between interval simulation and cycle-accurate simulation by enabling high-speed simulations with higher levels of detail. We also show that using accurate core models like these are important for memory subsystem studies, and that simple, naive models, like a one-IPC core model, can lead to misleading and incorrect results and conclusions in practical design studies. Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.
		+
		+	===DOI Link===
		+	[http://dx.doi.org/10.1145/2629677 DOI Link]

	===Bibtex entry===		===Bibtex entry===

@@ Line 1: / Line 1: @@
 {{DISPLAYTITLE:An Evaluation of High-Level Mechanistic Core Models}}
-Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
+Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout
 ''Published in the ACM Transactions on Architecture and Code Optimization ([http://taco.acm.org TACO])''