Difference between revisions of "Paper:Hpca2010Genbrugge"

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Line 24: Line 24:
 
   year = {2010},
 
   year = {2010},
 
   pages = {307--318},
 
   pages = {307--318},
   month = feb,
+
   month = feb
  abstract = {Detailed architectural simulators suffer from a long development cycle
 
and extremely long evaluation times. This longstanding problem is
 
further exacerbated in the multicore processor era. Existing solutions
 
address the simulation problem by either sampling the simulated instruction
 
stream or by mapping the simulation models on FPGAs; these approaches
 
achieve substantial simulation speedups while simulating performance
 
in a cycle-accurate manner.
 
 
This paper proposes interval simulation which takes a completely different
 
approach: interval simulation raises the level of abstraction and
 
replaces the core-level cycleaccurate simulation model by a mechanistic
 
analytical model. The analytical model estimates core-level performance
 
by analyzing intervals, or the timing between two miss events (branch
 
mispredictions and TLB/cache misses); the miss events are determined
 
through simulation of the memory hierarchy, cache coherence protocol,
 
interconnection network and branch predictor. By raising the level
 
of abstraction, interval simulation reduces both development time
 
and evaluation time.
 
 
Our experimental results using the SPEC CPU2000 and PARSEC benchmark
 
suites and the M5 multi-core simulator, show good accuracy up to
 
eight cores (average error of 4.6% and max error of 11% for the multi-threaded
 
fullsystem workloads), while achieving a one order of magnitude simulation
 
speedup compared to cycle-accurate simulation. Moreover, interval
 
simulation is easy to implement: our implementation of the mechanistic
 
analytical model incurs only one thousand lines of code. Its high
 
accuracy, fast simulation speed and ease-of-use make interval simulation
 
a useful complement to the architect’s toolbox for exploring system-level
 
and high-level micro-architecture trade-offs.}
 
 
}
 
}
 
</pre>
 
</pre>

Latest revision as of 05:38, 29 December 2011

Davy Genbrugge, Stijn Eyerman and Lieven Eeckhout

Published at the 16th International Symposium on High Performance Computer Architecture (HPCA-16), 2010

Abstract

Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This longstanding problem is further exacerbated in the multicore processor era. Existing solutions address the simulation problem by either sampling the simulated instruction stream or by mapping the simulation models on FPGAs; these approaches achieve substantial simulation speedups while simulating performance in a cycle-accurate manner.

This paper proposes interval simulation which takes a completely different approach: interval simulation raises the level of abstraction and replaces the core-level cycleaccurate simulation model by a mechanistic analytical model. The analytical model estimates core-level performance by analyzing intervals, or the timing between two miss events (branch mispredictions and TLB/cache misses); the miss events are determined through simulation of the memory hierarchy, cache coherence protocol, interconnection network and branch predictor. By raising the level of abstraction, interval simulation reduces both development time and evaluation time.

Our experimental results using the SPEC CPU2000 and PARSEC benchmark suites and the M5 multi-core simulator, show good accuracy up to eight cores (average error of 4.6% and max error of 11% for the multi-threaded fullsystem workloads), while achieving a one order of magnitude simulation speedup compared to cycle-accurate simulation. Moreover, interval simulation is easy to implement: our implementation of the mechanistic analytical model incurs only one thousand lines of code. Its high accuracy, fast simulation speed and ease-of-use make interval simulation a useful complement to the architect’s toolbox for exploring system-level and high-level micro-architecture trade-offs.

Full text

Full paper PDF

Bibtex entry

@INPROCEEDINGS{genbrugge2010isrtloaias,
  author = {Davy Genbrugge and Stijn Eyerman and Lieven Eeckhout},
  title = {Interval Simulation: Raising the Level of Abstraction in Architectural
	Simulation},
  booktitle = {Proceedings of the 16th IEEE International Symposium on High-Performance
	Computer Architecture (HPCA)},
  year = {2010},
  pages = {307--318},
  month = feb
}