Tutorial:ISPASS 2012

Tutorial Complete

We would like to thank the attendees of the tutorial and those we talked with at ISPASS for your interest in using and developing with Sniper. If there are any additional questions or ideas that you might have, please feel free to browse or post on our mailing list. The tutorial slides are now available online and can be downloaded below.

Slides

ISPASS Tutorial Slides

Location and Date

The Sniper Tutorial will be held at ISPASS 2012 in New Brunswick, NJ on Sunday, April 1st between 9am and 12pm.

Organizers and Presenters

Organizer: Lieven Eeckhout, Ghent University
Presenter: Wim Heirman, Intel ExaScience Lab and Ghent University
Presenter: Trevor E. Carlson, Intel ExaScience Lab and Ghent University

Abstract

Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast, scalable and accurate simulations are needed to allow for sufficient exploration of large multi-core systems within a limited simulation time budget. Through the use of high-abstraction analytical models with fast parallel simulation in the Sniper simulator, computer architects can trade off accuracy with simulation speed to allow for longer application runs, covering a larger portion of the hardware design space.

The purpose of this tutorial is to introduce both the main features of the Sniper simulator, as well as provide detail into the use of the simulator itself. Specifically, this tutorial will provide an in-depth look into the theory and implementation of the interval core model and CPI-stack generation. We will also highlight features like full DVFS support, scripting and program-to-simulator communication and provide an overview of the various component models and simulator configurability and flexibility.

Sniper's key features are:

• The interval core model to raise the level of abstraction in multi-core simulation
• Parallel simulation on multi-core host hardware
• Runs multi-threaded shared-memory x86 workloads
• Achieves good simulation speed, up to 2 MIPS
• Validated against real hardware

Additional information about Sniper can be found here.

Topics to be Covered

• Sniper simulator overview
• Interval Model in depth
• Simulator HW features and components
• Simulator SW features
  • DVFS control, scripting interfaces, etc.
• Validation results
• Hands-on demonstration

Biographies

Lieven Eeckhout is an Associate Professor at Ghent University, Belgium, in the Department of Electronics and Information Systems (ELIS). He obtained his MS and PhD degrees from Ghent University in 1998 and 2002, respectively. His research interests include computer architecture and the hardware/software interface in general, and performance analysis, evaluation and modeling more in particular. He received two IEEE Micro Top Picks Awards and recently wrote a synthesis lecture on "Computer Architecture Performance Evaluation Methods" published by Morgan and Claypool. He graduated 7 PhD students, and currently supervises 4 postdoctoral researchers and 8 PhD students.

Wim Heirman received his PhD in 2008 from Ghent University, Belgium, on reconfigurable optical interconnection networks for multicore processors. Since 2010 he works at the Intel Exascience Lab. His research interests are fast and accurate computer simulation, enabling architectural exploration and software analysis through co-design, and energy-efficient high-performance computing.

Trevor E. Carlson is a PhD student at Ghent University and is a part of the Intel ExaScience Lab. He received his BS and MS degrees from Carnegie Mellon University in 2002 and 2003, respectively. He has previously served as a Staff Engineer at IBM where he helped to author 4 issued patents and also served as a Researcher at IMEC where he investigated efficient architectures for embedded and 3D-stacked systems. His research interests include performance modeling and fast and scalable simulation methodologies.