Difference between revisions of "Paper:Pact2012Heirman"
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To enable hardware/software co-design in early stages of the design cycle, we propose a novel simulation infrastructure by combining high-abstraction performance simulation using Sniper with power modeling using McPAT and custom DRAM power models. Sniper/McPAT is fast --- simulation speed is around 2 MIPS on an 8-core host machine --- because it uses analytical modeling to abstract away core performance during multi-core simulation. We demonstrate Sniper/McPAT's accuracy through validation against real hardware; we report average performance and power prediction errors of 22.1% and 8.3%, respectively, for a set of SPEComp benchmarks. | To enable hardware/software co-design in early stages of the design cycle, we propose a novel simulation infrastructure by combining high-abstraction performance simulation using Sniper with power modeling using McPAT and custom DRAM power models. Sniper/McPAT is fast --- simulation speed is around 2 MIPS on an 8-core host machine --- because it uses analytical modeling to abstract away core performance during multi-core simulation. We demonstrate Sniper/McPAT's accuracy through validation against real hardware; we report average performance and power prediction errors of 22.1% and 8.3%, respectively, for a set of SPEComp benchmarks. | ||
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| − | [http://www.exascience.com/wp-content/uploads/ | + | [http://www.exascience.com/wp-content/uploads/2012/08/Heirman-Pact2012.pdf Full paper PDF] |
===Bibtex entry=== | ===Bibtex entry=== | ||
Latest revision as of 10:03, 8 August 2012
Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout
International Conference on Parallel Architectures and Compilation Techniques (PACT 2012)
Abstract
Stringent performance targets and power constraints push designers towards building specialized workload-optimized systems across a broad spectrum of the computing arena, including supercomputing applications as exemplified by the IBM BlueGene and Intel MIC architectures. In this paper, we make the case for hardware/software co-design during early design stages of processors for scientific computing applications. Considering an important scientific kernel, namely stencil computation, we demonstrate that performance and energy-efficiency can be improved by a factor of 1.66x and 1.25x, respectively, by co-optimizing hardware and software.
To enable hardware/software co-design in early stages of the design cycle, we propose a novel simulation infrastructure by combining high-abstraction performance simulation using Sniper with power modeling using McPAT and custom DRAM power models. Sniper/McPAT is fast --- simulation speed is around 2 MIPS on an 8-core host machine --- because it uses analytical modeling to abstract away core performance during multi-core simulation. We demonstrate Sniper/McPAT's accuracy through validation against real hardware; we report average performance and power prediction errors of 22.1% and 8.3%, respectively, for a set of SPEComp benchmarks.
Full text
Bibtex entry
@INPROCEEDINGS{heirman2012pmsfedshc,
author = {Wim Heirman and Souradip Sarkar and Trevor E. Carlson and Ibrahim Hur and Lieven Eeckhout},
title = {Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization},
booktitle = {International Conference on Parallel Architectures and Compilation Techniques (PACT)},
year = {2012},
month = sep
}
