Difference between revisions of "The Sniper Multi-Core Simulator"

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'''January 19th:''' We presented our [[Paper:Taco2014Carlson|TACO paper]] at the [https://www.hipeac.org/2015/amsterdam/ HiPEAC Conference] in Amsterdam.
'''June 15th:''' [https://sites.google.com/site/pinpointstutorialisca14 PinPoints Tutorial at ISCA] with Sniper. Learn about PinPoints or [[Pinballs|download SPEC CPU2006 pinballs]]
'''June 15th:''' [https://sites.google.com/site/pinpointstutorialisca14 PinPoints Tutorial at ISCA] with Sniper. Learn about PinPoints or [[Pinballs|download SPEC CPU2006 pinballs]]
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'''September 22nd:''' [[Tutorial:IISWC_2013_Sniper|Sniper tutorial at IISWC]]
'''September 22nd:''' [[Tutorial:IISWC_2013_Sniper|Sniper tutorial at IISWC]]
'''April 23rd:''' Our [[Paper:Ispass2013Carlson|recent work on multi-threaded sampled simulation]] ([http://www.exascience.com/wp-content/uploads/2013/02/Carlson-Sampled-simulation.pdf paper]|[http://www.snipersim.org/documents/presentations/2013-04-22%20ISPASS%20Multi-threaded%20Sampling.pdf presentation]) won the [http://ispass.org/ispass2013 ISPASS 2013 Best Paper Award]

Revision as of 02:20, 26 January 2015

January 19th: We presented our TACO paper at the HiPEAC Conference in Amsterdam.

June 15th: PinPoints Tutorial at ISCA with Sniper. Learn about PinPoints or download SPEC CPU2006 pinballs

June 3rd: Sniper 6.0 released with detailed core model supporting in-order, out-of-order and SMT cores

February 10th: The FOSDEM 2014 video of the Sniper tutorial is now available to view

September 22nd: Sniper tutorial at IISWC

Sniper is a next generation parallel, high-speed and accurate x86 simulator. This multi-core simulator is based on the interval core model and the Graphite simulation infrastructure, allowing for fast and accurate simulation and for trading off simulation speed for accuracy to allow a range of flexible simulation options when exploring different homogeneous and heterogeneous multi-core architectures.

The Sniper simulator allows one to perform timing simulations for both multi-program workloads and multi-threaded, shared-memory applications with 10s to 100+ cores, at a high speed when compared to existing simulators. The main feature of the simulator is its core model which is based on interval simulation, a fast mechanistic core model. Interval simulation raises the level of abstraction in architectural simulation which allows for faster simulator development and evaluation times; it does so by 'jumping' between miss events, called intervals. Sniper has been validated against multi-socket Intel Core2 and Nehalem systems and provides average performance prediction errors within 25% at a simulation speed of up to several MIPS.

This simulator, and the interval core model, is useful for uncore and system-level studies that require more detail than the typical one-IPC models, but for which cycle-accurate simulators are too slow to allow workloads of meaningful sizes to be simulated. As an added benefit, the interval core model allows the generation of CPI stacks, which show the number of cycles lost due to different characteristics of the system, like the cache hierarchy or branch predictor, and leads to a better understanding of each component's effect on total system performance. This extends the use for Sniper to application characterization and hardware/software co-design.


CPI stack visualization in Sniper 4.1
IPC visualization in Sniper 4.1

In addition to the main features mentioned above, we have updated the base simulation infrastructure to allow for simulating a larger set of workloads on more recent simulated hardware. Here is the full set of some of the recently added features:

  • Interval core model
  • Instruction-Window Centric core model, supporting in-order, out-of-order and SMT cores
  • Multi-threaded application sampling support
  • CPI Stacks and advanced visualization support to gain insight into lost cycles
  • Parallel, multi-threaded simulator
  • Multi-program and multi-threaded application support, x86 and x86-64, SSE2
  • Validated against the Intel Core 2 microarchitecture (See the FAQ for details)
  • Full DVFS support
  • Shared and private caches
  • Prefetchers
  • Scheduling support
  • Heterogeneous configuration support
  • Modern branch predictor
  • Supports parallel applications using pthreads, OpenMP, TBB, OpenCL
  • Runs SPLASH-2, Rodinia, SPEC OMP and most of PARSEC (See our integrated benchmarks quick-start guide)
  • McPAT integration
  • SimAPI and Python interfaces for monitoring and controlling the simulator's behavior at runtime
  • Single-option debugging of simulator or the application itself
  • Modern Linux-OS support (Redhat EL 5,6/Debian Lenny+/Ubuntu 10.04-14.04+/etc.)
  • Open source software, licensed under the MIT and the Interval Academic License
  • Additional features

You can find additional information on the simulator and its components in our TACO or SC'11 paper.

Getting started

Discussion list

Subscribe to the Snipersim mailing list

Please send any questions or comments to: snipersim [at] googlegroups [dot] com . You can also visit our Google Groups page to subscribe to the list and search through the archive of previous messages.

Team Members

More information

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