Difference between revisions of "The Sniper Multi-Core Simulator"

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Sniper 8.0 is now available on [https://github.com/snipersim/snipersim GitHub] and [https://hub.docker.com/r/snipersim/snipersim DockerHub]
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Version 7.3 of [[Releases|Sniper has been released]]. It has support for Ubuntu 18.04, GCC 7, Pin 3.10+, and [https://carrv.github.io/2018/papers/CARRV_2018_paper_7.pdf initial support for RISC-V].
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'''April 1st:''' [[Tutorial:ISPASS 2012|Sniper tutorial at ISPASS'12]]
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An initial implementation of [https://github.com/trevorcarlson/barrierpoint BarrierPoint] had been released.
 +
 
 +
[https://sites.google.com/site/pinpointstutorialisca14 PinPoints Tutorial at ISCA] with Sniper. Learn about PinPoints or [[Pinballs|download SPEC CPU2006 pinballs]]
 +
 
 +
The FOSDEM 2014 video of the Sniper tutorial is [[FOSDEM_2014|now available to view]]
 +
 
 +
[[Tutorial:IISWC_2013_Sniper|Sniper tutorial at IISWC]]
  
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'''June 9th:''' [[Tutorial:ISCA 2012|Sniper tutorial at ISCA'12]]
 
 
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[[Paper:Sc2011Carlson|Sniper]] is
 
[[Paper:Sc2011Carlson|Sniper]] is
 
a next generation parallel, high-speed and accurate
 
a next generation parallel, high-speed and accurate
−
x86-64 simulator.  This multi-core simulator is
+
x86 simulator.  This multi-core simulator is
−
based on the [[Interval Simulation|interval core model]] and the [http://groups.csail.mit.edu/carbon/graphite Graphite] simulation
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based on the [[Interval Simulation|interval core model]] and the [https://github.com/mit-carbon/Graphite Graphite] simulation
 
infrastructure, allowing for fast and accurate simulation and for
 
infrastructure, allowing for fast and accurate simulation and for
 
trading off simulation speed for accuracy to allow a range of flexible
 
trading off simulation speed for accuracy to allow a range of flexible
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simulation options when exploring different multi-core architectures.
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simulation options when exploring different homogeneous and heterogeneous multi-core architectures.
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Using this methodology, we are able to achieve good
 
−
accuracy against hardware for 16-thread applications.
 
  
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The Sniper simulator allows one to perform timing simulations for
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The Sniper simulator allows one to perform timing simulations for both multi-program workloads
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multi-threaded, shared-memory applications with 10s to 100+ cores,
+
and multi-threaded, shared-memory applications with 10s to 100+ cores,
 
at a high speed when compared to existing simulators.  The main
 
at a high speed when compared to existing simulators.  The main
−
feature of the simulator is its core model which is based on the [[Interval Simulation|interval core model]],
+
feature of the simulator is its core model which is based on [[Interval Simulation|interval simulation]],
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a fast mechanistic core model. The interval model raises the level
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a fast mechanistic core model. Interval simulation raises the level
 
of abstraction in architectural simulation which allows for faster
 
of abstraction in architectural simulation which allows for faster
 
simulator development and evaluation times; it does so by 'jumping'
 
simulator development and evaluation times; it does so by 'jumping'
−
between miss events, called intervals. On recent multi-core hardware,
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between miss events, called intervals.
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we see speeds of up to 2 MIPS
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Sniper has been validated against multi-socket Intel Core2 and Nehalem systems
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for SPLASH-2 benchmarks, and almost 3 MIPS for SPEC OMP benchmarks.
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and provides average performance prediction errors within 25%
 +
at a simulation speed of up to several MIPS.
  
 
This simulator, and the interval core model, is useful for uncore
 
This simulator, and the interval core model, is useful for uncore
 
and system-level studies that require more detail than the typical
 
and system-level studies that require more detail than the typical
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one-IPC models. As an added benefit, the interval core model allows
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one-IPC models, but for which cycle-accurate
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the generation of CPI stacks, which shows the number of cycles lost
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simulators are too slow to allow workloads of meaningful sizes to be simulated.
 +
As an added benefit, the interval core model allows
 +
the generation of CPI stacks, which show the number of cycles lost
 
due to different characteristics of the system, like the cache
 
due to different characteristics of the system, like the cache
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hierarchy or branch predictor, to be easily understood.
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hierarchy or branch predictor, and leads to a better understanding of each component's
 +
effect on total system performance. This extends the use for Sniper
 +
to application characterization and hardware/software co-design.
  
 
=== Features ===
 
=== Features ===
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<div class="floatright">http://snipersim.org/w/images/cpi-splash2-fft-lg.png</div>
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[[File:Level2vis400.png|right|CPI stack visualization in Sniper 4.1|link=http://snipersim.org/viz/fft-tiny-4/levels/level2/cyclestacks.html]]
 +
[[File:Level3vis400.png|right|IPC visualization in Sniper 4.1|link=http://snipersim.org/viz/fft-tiny-4/levels/level3/level3.html]]
 
In addition to the main features mentioned above, we have updated
 
In addition to the main features mentioned above, we have updated
 
the base simulation infrastructure to allow for simulating a larger
 
the base simulation infrastructure to allow for simulating a larger
Line 52: Line 54:
 
set of some of the recently added features:
 
set of some of the recently added features:
 
* [[Interval Simulation|Interval core model]]
 
* [[Interval Simulation|Interval core model]]
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* [[CPI Stacks]] to gain insight into lost cycles
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* [[Paper:Taco2014Carlson|Instruction-Window Centric core model, supporting in-order, out-of-order and SMT cores]]
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* Parallel, multithreaded simulator
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* [[Paper:Ispass2013Carlson|Multi-threaded application sampling support]]
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* Multithreaded application support, x86-64, SSE2
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* [[CPI Stacks]] and [http://snipersim.org/viz/fft-tiny-4/ advanced visualization support] to gain insight into lost cycles
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* Validated against the Intel Core 2 and Nehalem/Westmere microarchitectures
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* Parallel, multi-threaded simulator
 +
* [[Multi-programmed workloads|Multi-program]] and multi-threaded application support, x86 and x86-64, SSE2
 +
* Validated against the Intel Core 2 microarchitecture (See the [[Frequently Asked Questions|FAQ]] for details)
 
* Full DVFS support
 
* Full DVFS support
 
* Shared and private caches
 
* Shared and private caches
 +
* Prefetchers
 +
* Scheduling support
 +
* [[Heterogeneous Configuration|Heterogeneous configuration support]]
 
* [http://dx.doi.org/10.1109/ISPASS.2009.4919652 Modern branch predictor]
 
* [http://dx.doi.org/10.1109/ISPASS.2009.4919652 Modern branch predictor]
 
* Supports parallel applications using pthreads, OpenMP, TBB, OpenCL
 
* Supports parallel applications using pthreads, OpenMP, TBB, OpenCL
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* Runs SPLASH-2, Rodinia, SPEC OMP and most of PARSEC
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* Runs SPLASH-2, Rodinia, SPEC OMP and most of PARSEC (See our [[Download Benchmarks|integrated benchmarks quick-start guide]])
 +
* [[McPAT]] integration
 
* SimAPI and Python interfaces for monitoring and controlling the simulator's behavior at runtime
 
* SimAPI and Python interfaces for monitoring and controlling the simulator's behavior at runtime
 
* Single-option debugging of simulator or the application itself
 
* Single-option debugging of simulator or the application itself
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* Multiple Linux-OS support (Redhat/Debian/Ubuntu/etc.)
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* Modern Linux-OS support (Redhat EL 5,6/Debian Lenny+/Ubuntu 10.04-15.04+/etc.)
 
* Open source software, [[License|licensed]] under the MIT and the Interval Academic License
 
* Open source software, [[License|licensed]] under the MIT and the Interval Academic License
 
* [[Sniper Features|Additional features]]
 
* [[Sniper Features|Additional features]]
  
−
You can find additional information on the simulator and its components in our [[Paper:Sc2011Carlson|SC'11 paper]].
+
You can find additional information on the simulator and its components in our [[Paper:Taco2014Carlson|TACO]] or [[Paper:Sc2011Carlson|SC'11 paper]].
  
 
=== Getting started ===
 
=== Getting started ===
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* [[Download]] the Sniper source code (Git and download options)
 
* [[Download]] the Sniper source code (Git and download options)
 
* Follow the [[Getting Started]] instructions
 
* Follow the [[Getting Started]] instructions
 +
* Take a look at the [[Manual|Sniper Manual]]
 
* View the [[Frequently Asked Questions]]
 
* View the [[Frequently Asked Questions]]
−
* Attend our tutorial at [[Tutorial:ISPASS 2012|ISPASS'12]] or [[Tutorial:ISCA_2012|ISCA'12]]
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* Review the [http://snipersim.org/documents/2013-01-22%20Sniper%20HiPEAC%20Tutorial.pdf slides from our latest tutorial]
 +
* View our most recent [[Releases|simulator updates]]
 +
* If you are using a modern version of Sniper, please cite our [[Paper:Taco2014Carlson|TACO paper (bibtex)]]
  
 
=== Discussion list ===
 
=== Discussion list ===
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   <b>Subscribe to the Snipersim mailing list</b>
 
   <b>Subscribe to the Snipersim mailing list</b>
 
   </td></tr>
 
   </td></tr>
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   <form action="http://groups.google.com/group/snipersim/boxsubscribe">
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   <form action="https://groups.google.com/group/snipersim/boxsubscribe">
 
   <tr><td style="padding-left: 5px;">
 
   <tr><td style="padding-left: 5px;">
 
   Email: <input type=text name=email>
 
   Email: <input type=text name=email>
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=== Team Members ===
 
=== Team Members ===
−
* [http://www.elis.ugent.be/~tcarlson Trevor E. Carlson] with the [http://exascience.com Intel ExaScience Lab] and [http://www.ugent.be Ghent University]
+
* [https://comp.nus.edu.sg/~tcarlson Trevor E. Carlson] with [http://nus.edu.sg National University of Singapore]
−
* [http://www.elis.ugent.be/~wheirman Wim Heirman] with the [http://exascience.com Intel ExaScience Lab] and [http://www.ugent.be Ghent University]
+
* [http://www.elis.ugent.be/~wheirman Wim Heirman] with the [http://exascience.com Intel ExaScience Lab]
 
* [http://www.elis.ugent.be/~leeckhou Lieven Eeckhout] with [http://www.ugent.be Ghent University]
 
* [http://www.elis.ugent.be/~leeckhou Lieven Eeckhout] with [http://www.ugent.be Ghent University]
−
* [mailto:ibrahim.hur@intel.com Ibrahim Hur] with Intel
+
* [mailto:ibrahim.hur@intel.com Ibrahim Hur] with the [http://exascience.com Intel ExaScience Lab]
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* [mailto:mazhe@imec.be Ma Zhe] with [http://www.imec.be imec]
 
  
 
=== More information ===
 
=== More information ===
Line 105: Line 115:
 
* [[Sniper Tutorials]]
 
* [[Sniper Tutorials]]
  
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<meta name="keywords" content="Sniper Simulator,Sniper,simulator,computer architecture,multicore,multi core,multi-core,manycore,many core,many-core,micro-architecture,microarchitecture,ExaScience Lab,exascience,exascale,SC11,supercomputers,super-computing,computers,Ghent University,Universiteit Gent"/>
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<metadesc>Sniper Simulator,Sniper,simulator,computer architecture,multicore,multi core,multi-core,manycore,many core,many-core,micro-architecture,microarchitecture,ExaScience Lab,exascience,exascale,SC11,supercomputers,super-computing,computers,Ghent University,Universiteit Gent</metadesc>
  
 
__NOTOC__
 
__NOTOC__

Latest revision as of 17:55, 5 September 2023

Sniper 8.0 is now available on GitHub and DockerHub

Version 7.3 of Sniper has been released. It has support for Ubuntu 18.04, GCC 7, Pin 3.10+, and initial support for RISC-V.

An initial implementation of BarrierPoint had been released.

PinPoints Tutorial at ISCA with Sniper. Learn about PinPoints or download SPEC CPU2006 pinballs

The FOSDEM 2014 video of the Sniper tutorial is now available to view

Sniper tutorial at IISWC

Sniper is a next generation parallel, high-speed and accurate x86 simulator. This multi-core simulator is based on the interval core model and the Graphite simulation infrastructure, allowing for fast and accurate simulation and for trading off simulation speed for accuracy to allow a range of flexible simulation options when exploring different homogeneous and heterogeneous multi-core architectures.

The Sniper simulator allows one to perform timing simulations for both multi-program workloads and multi-threaded, shared-memory applications with 10s to 100+ cores, at a high speed when compared to existing simulators. The main feature of the simulator is its core model which is based on interval simulation, a fast mechanistic core model. Interval simulation raises the level of abstraction in architectural simulation which allows for faster simulator development and evaluation times; it does so by 'jumping' between miss events, called intervals. Sniper has been validated against multi-socket Intel Core2 and Nehalem systems and provides average performance prediction errors within 25% at a simulation speed of up to several MIPS.

This simulator, and the interval core model, is useful for uncore and system-level studies that require more detail than the typical one-IPC models, but for which cycle-accurate simulators are too slow to allow workloads of meaningful sizes to be simulated. As an added benefit, the interval core model allows the generation of CPI stacks, which show the number of cycles lost due to different characteristics of the system, like the cache hierarchy or branch predictor, and leads to a better understanding of each component's effect on total system performance. This extends the use for Sniper to application characterization and hardware/software co-design.

Features

CPI stack visualization in Sniper 4.1
IPC visualization in Sniper 4.1

In addition to the main features mentioned above, we have updated the base simulation infrastructure to allow for simulating a larger set of workloads on more recent simulated hardware. Here is the full set of some of the recently added features:

You can find additional information on the simulator and its components in our TACO or SC'11 paper.

Getting started

Discussion list

Subscribe to the Snipersim mailing list
Email:

Please send any questions or comments to: snipersim [at] googlegroups [dot] com . You can also visit our Google Groups page to subscribe to the list and search through the archive of previous messages.

Team Members

More information



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