The Sniper Multi-Core Simulator
Version 7.3 of Sniper has been released. It has support for Ubuntu 18.04, GCC 7, Pin 3.10+, and initial support for RISC-V.
An initial implementation of BarrierPoint had been released.
PinPoints Tutorial at ISCA with Sniper. Learn about PinPoints or download SPEC CPU2006 pinballs
The FOSDEM 2014 video of the Sniper tutorial is now available to view
Sniper is a next generation parallel, high-speed and accurate x86 simulator. This multi-core simulator is based on the interval core model and the Graphite simulation infrastructure, allowing for fast and accurate simulation and for trading off simulation speed for accuracy to allow a range of flexible simulation options when exploring different homogeneous and heterogeneous multi-core architectures.
The Sniper simulator allows one to perform timing simulations for both multi-program workloads and multi-threaded, shared-memory applications with 10s to 100+ cores, at a high speed when compared to existing simulators. The main feature of the simulator is its core model which is based on interval simulation, a fast mechanistic core model. Interval simulation raises the level of abstraction in architectural simulation which allows for faster simulator development and evaluation times; it does so by 'jumping' between miss events, called intervals. Sniper has been validated against multi-socket Intel Core2 and Nehalem systems and provides average performance prediction errors within 25% at a simulation speed of up to several MIPS.
This simulator, and the interval core model, is useful for uncore and system-level studies that require more detail than the typical one-IPC models, but for which cycle-accurate simulators are too slow to allow workloads of meaningful sizes to be simulated. As an added benefit, the interval core model allows the generation of CPI stacks, which show the number of cycles lost due to different characteristics of the system, like the cache hierarchy or branch predictor, and leads to a better understanding of each component's effect on total system performance. This extends the use for Sniper to application characterization and hardware/software co-design.
In addition to the main features mentioned above, we have updated the base simulation infrastructure to allow for simulating a larger set of workloads on more recent simulated hardware. Here is the full set of some of the recently added features:
- Interval core model
- Instruction-Window Centric core model, supporting in-order, out-of-order and SMT cores
- Multi-threaded application sampling support
- CPI Stacks and advanced visualization support to gain insight into lost cycles
- Parallel, multi-threaded simulator
- Multi-program and multi-threaded application support, x86 and x86-64, SSE2
- Validated against the Intel Core 2 microarchitecture (See the FAQ for details)
- Full DVFS support
- Shared and private caches
- Scheduling support
- Heterogeneous configuration support
- Modern branch predictor
- Supports parallel applications using pthreads, OpenMP, TBB, OpenCL
- Runs SPLASH-2, Rodinia, SPEC OMP and most of PARSEC (See our integrated benchmarks quick-start guide)
- McPAT integration
- SimAPI and Python interfaces for monitoring and controlling the simulator's behavior at runtime
- Single-option debugging of simulator or the application itself
- Modern Linux-OS support (Redhat EL 5,6/Debian Lenny+/Ubuntu 10.04-15.04+/etc.)
- Open source software, licensed under the MIT and the Interval Academic License
- Additional features
You can find additional information on the simulator and its components in our TACO or SC'11 paper.
- Download the Sniper source code (Git and download options)
- Follow the Getting Started instructions
- Take a look at the Sniper Manual
- View the Frequently Asked Questions
- Review the slides from our latest tutorial
- View our most recent simulator updates
- If you are using a modern version of Sniper, please cite our TACO paper (bibtex)
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- Trevor E. Carlson with National University of Singapore
- Wim Heirman with the Intel ExaScience Lab
- Lieven Eeckhout with Ghent University
- Ibrahim Hur with the Intel ExaScience Lab